1. Technical Field
The present disclosure relates to circuit topologies, and particularly to a circuit topology for multiple loads on a motherboard.
2. Description of Related Art
With the increasing speeds of integrated circuits (ICs), signal integrity is becoming one of the most pressing problems. Many factors, such as the parameters of the electrical elements of a printed circuit board (PCB) and the layout of the PCB, can affect the signal integrity, or lead to instability of the system, possibly even causing a system including the PCB to breakdown. Thus, preserving signal integrity has become a key point in the design of a PCB.
Referring to FIG. 3, a related-art circuit topology 80 of a system includes a driving terminal 10 coupled to six loads 20, 30, 40, 50, 60, and 70, such as integrated circuits (ICs), via corresponding transmission lines 11, 12, 13, 14, 15, and 16. The six loads 20, 30, 40, 50, 60, and 70 are connected in parallel with the driving terminal 10. In this circuit topology 80, a driving signal from the driving terminal 10 is divided into six transmitting paths to the six loads 20, 30, 40, 50, 60, and 70 respectively. Because the transmitting paths of the driving signal are not consecutive, impedances of the transmission lines 11, 12, 13, 14, 15, and 16 may not match the driving signal. Therefore, the driving signal may generate some noise signals on the transmission lines 11, 12, 13, 14, 15, and 16, which may make a voltage of the system overshoot or undershoot a standard range, and may even generate a non-monotonic phenomenon.
Referring to FIG. 4, a graph illustrating signal waveforms respectively obtained at the six loads 20, 30, 40, 50, 60, and 70 using the circuit topology 80 of FIG. 3 is shown. Some signal waveforms have non-monotonic phenomenon between 90 ns to 100 ns. The range of the actual system voltage is between −0.8V to 4V, over the standard voltage range 0V to 3.3V, which may reduce signal integrity and may damage the loads 20, 30, 40, 50, 60, and 70.